The present invention relates generally to the protection of integrated circuits against electrostatic discharge (ESD) voltage events and, more particularly, to methods of stress testing of silicon-on-insulator (SOI) substrates using applied electrostatic discharge.
The progression of integrated circuit technology has led to the scaling of transistors to enable faster transistors operating at lower supply voltages. In complementary metal oxide semiconductor (CMOS) applications, the faster transistors require the use of very thin gate oxides and shorter channel lengths in order to obtain higher drive currents. The gate oxide thickness, for instance, has decreased from approximately 5.0 nanometers (nm) in 0.25 micron (μm) technology to approximately 1.5 nm in 90 nm technology, and is expected to decrease even further in future technologies. The thinner gate oxides are more susceptible to failure under random ESD voltages due to their smaller breakdown voltages.
The problem of ESD voltage events occurring on input/output (I/O) pins of an integrated circuit has been addressed in many ways. Most common is the use of an ESD protection device connected to the input/output pad of an integrated circuit to safely discharge ESD currents to ground before they can damage any of the connected circuitry. ESD events may be generally characterized by a human body model (HBM), a charged device model (CDM), or a machine model (MM). Different ESD models correspond to different current pulse waveforms and different peak currents.
It is important to manufacturers of electronic equipment to understand the susceptibility of such equipment to damage from electrostatic discharge. ESD testing typically involves simulating a human finger approaching an electronic device under test (DUT). An ESD probe is manually displaced toward a DUT which has been placed on a metal table, connected to ground. The results of ESD testing can be of value to manufacturers in improving such products so that they are less susceptible to damage.